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PM6681A
Dual step-down controller with adjustable LDO
Target Specification
Features

6V to 36V input voltage range Adjustable output voltages 0.9-3.3V LDO adjustable delivers 100mA peak current 5V LDO delivers 100mA peak current 1.237V 1% reference voltage available NO RSENSE current sensing using low side MOSFETs' RDS(on) Negative current limit Soft start internally fixed at 2ms Soft output discharge Latched UVP Not-latched OVP Selectable pulse skipping at light loads Selectable minimum frequency(33kHz) in pulse skip mode 5mW maximum quiescent power Indipendent power good signals Output voltage ripple compensation PM6681A is a dual step-down controller specifically designed to provide extremely high efficiency conversion, with lossless current sensing technique. The constant on-time architecture assures fast load transient response and the embedded voltage feed-forward provides nearly constant switching frequency operation. An embedded integrator control loop compensates the DC voltage error due to the output ripple. Pulse skipping technique increases efficiency at very light load. Moreover a minimum switching frequency of 33kHz is selectable to avoid audio noise issues. The PM6681A provides a selectable switching frequency, allowing three different values of switching frequencies for the two switching sections. The output voltages OUT1 and OUT2 can be adjusted from 0.9V to 5V and from 0.9V to 3.3V respectively. The device provides also 2 LDOs, 5V fixed and 0.9V-3.3V adjustable.
VFQFPN-32 (5mm x 5mm)
Description

Applications

Embedded computer system FPGA system power Industrial applications on 24V High performance and high density DC/DC modules
Order codes
Part number PM6681A PM6681ATR November 2006 Package VFQFPN-32 (5mm x 5mm) VFQFPN-32 (5mm x 5mm) Rev 1 Packaging Tube Tape and Reel 1/12
www.st.com 12
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
Contents
PM6681A
Contents
1 2 Simplified application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 4 5
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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1
PM6681A
Figure 1.
V+ BOOT1
+
V+ BOOT2 31 18 19 SGND U1 PGND BOOT2 HGATE2 PHASE2 LGATE2 CSENSE2 PGND 14 1 SGND 8 2 6 28 FB1 7 PGND PGND 12 13 1 OUT211 10 1 SGND 9 VCC LDO5 VIN SGND VIN
VIN
23 BOOT1 HGATE1 PHASE1 LGATE1 CSENSE1 V5SW OUT1 COMP1 LDO FB PGOOD1 PGOOD2 SHDN LDO FB1 FB2 COMP2 OUT2 22 21 15 20 PGND SGND 29 SGND 30 LDO FB 26 27 5 PGOOD1 EN2 EN1 VREF SKIP FSEL PGOOD2 16 17
PGND
1
OUT1+
+
OUT2+
+
Simplified application schematic
1
OUT1-
PM6681A PM6681
V+ V+
Simplified application schematic
SGND
FB1
SGND
LDO FB
4
25
32
24 3
SGND
SGND
SGND
SGND
Simplified application schematic
3/12
Pin settings
PM6681A
2
2.1
Pin settings
Connections
Figure 2. Pin connection (top view)
PG O O D2
PG O O D
CO M P1
VR EF 32 31
O UT
VCC 30
EN1
FB1
29
28
27
26
25
1 SG N D 2 C O M P2 FSEL 3
24 SK IP 23 B O OT 1 22 H G AT E1
4 EN 2 5 SH D N 6
21
PM 6681A
20 19
PH ASE1
C SEN S E1
FB2
VIN 7 18 LD O 5 8 17 V5SW 9 10 11 12 13 14 15 16
LDO
O U T2
LDO FB
HG ATE2
PHASE2
CSEN S E2
LG ATE2
PG ND
LG ATE1
BO O T2
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PM6681A
Pin settings
2.2
Functions
Table 1.
N
Pin functions
Pin Function Signal ground. Reference for internal logic circuitry. It must be connected to the signal ground plan of the power supply. The signal ground plan and the power ground plan must be connected together in one point near the PGND pin. DC voltage error compensation pin for the switching section 2 Frequency selection pin. It provides a selectable switching frequency, allowing three different values of switching frequencies for the switching sections. Enable input for the switching section 2. - The section 2 is enabled applying a voltage greater than 2.4V to this pin. - The section 2 is disabled applying a voltage lower than 0.8V. When the section is disabled the High Side gate driver goes low and Low Side gate driver goes high. If both EN1 and EN2 pins are low and SHDN pin is high the device enters in standby mode. Shutdown control input. - The device switch off if the SHDN voltage is lower than the device off thershold (Shutdown mode) - The device switch on if the SHDN voltage is greater than the device on threshold. The SHDN pin can be connected to the battery through a voltage divider to program an undervoltage lockout. In shutdown mode, the gate drivers of the two switching sections are in high impedance (high-Z). Feedback input for the switching section 2 This pin is connected to a resistive voltage-divider from OUT2 to PGND to adjust the output voltage from 0.9V to 3.3V. Adjustable internal regulator output. It can be set from 0.9V to 3.3V. LDO pin can provide a 100mA peak current. Output voltage sense for the switching section 2.This pin must be directly connected to the output votage of the switching section. Bootstrap capacitor connection for the switching section 2. It supplies the high-side gate driver. High-side gate driver ouput for section 2. This is the floating gate driver output. Switch node connection and return path for the high side driver for the section 2. It is also used as negative current sense input. Positive current sense input for the switching section 2. This pin must be connected through a resistor to the drain of the synchronous rectifier to obtain a positive current limit threshold for the power supply controller. Low-side gate driver output for the section 2. Power ground. This pin must be connected to the power ground plan of the power supply. Low-side gate driver output for the section 1.
1
SGND1
2 3
COMP2 FSEL
4
EN2
5
SHDN
6
FB2
7 8 9 10 11
LDO OUT2 BOOT2 HGATE2 PHASE2
12 13 14 15
CSENSE2 LGATE2 PGND LGATE1
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Pin settings Table 1.
N 16
PM6681A Pin functions (continued)
Pin LDO FB Function Feedback input for the adjustable internal linear regulator. This pin is connected to a resistive voltage-divider from LDO to SGND to adjust the output voltage from 0.9V to 3.3V. Internal 5V regulator bypass connection. - If V5SW is connected to OUT5 (or to an external 5V supply) and V5SW is greater than 4.9V, the LDO5 regulator shuts down and the LDO5 pin is directly connected to OUT5 through a 3W (max) switch. If V5SW is connected to GND, the LDO5 linear regulator is always on. 5V internal regulator output. It can provide up to 100mA peak current. LDO5 pin supplies embedded low side gate drivers and an external load. Device supply voltage input and battery voltage sense. A bypass filter (4 and 4.7mF) between the battery and this pin is recommended. Positive current sense input for the switching section 1. This pin must be connected through a resistor to the drain of the synchronous rectifier to obtain a positive current limit threshold for the power supply controller. Switch node connection and return path for the high side driver for the section 1.It is also used as negative current sense input. High-side gate driver ouput for section 1. This is the floating gate driver output. Bootstrap capacitor connection for the switching section 1. It supplies the high-side gate driver. Pulse skipping mode control input. - If the pin is connected to LDO5 the PWM mode is enabled. - If the pin is connected to GND, the pulse skip mode is enabled. - If the pin is connected to VREF the pulse skip mode is enabled but the switching frequency is kept higher than 33KHz (No-audible puse skip mode). Enable input for the switching section 1. - The section 1 is enabled applying a voltage greater than 2.4V to this pin. - The section 1 is disabled applying a voltage lower than 0.8V. When the section is disabled the High Side gate driver goes low and Low Side gate driver goes high. Power Good ouput signal for the section 1. This pin is an open drain ouput and when the ouput of the switching section 1 is out of +/- 10% of its nominal value.It is pulled down. Power Good ouput signal for the section 2. This pin is an open drain ouput and when the ouput of the switching section 2 is out of +/- 10% of its nominal value.It is pulled down. Feedback input for the switching section 1. This pin is connected to a resistive voltage-divider from OUT1 to PGND to adjust the output voltage from 0.9V to 5.5V. Output voltage sense for the switching section 1.This pin must be directly connected to the output votage of the switching section.
17
V5SW
18 19
LDO5 VIN
20
CSENSE1
21 22 23
PHASE1 HGATE1 BOOT1
24
SKIP
25
EN1
26
PGOOD1
27
PGOOD2
28
FB1
29
OUT1
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PM6681A Table 1.
N 30 31 32
Pin settings Pin functions (continued)
Pin COMP1 VCC VREF Function DC voltage error compensation pin for the switching section 1. Device Supply Voltage pin. It supplies all the internal analog circuitry except the gate drivers (see LDO5). Connect this pin to LDO5. Internal 1.237V high accuracy voltage reference. It can deliver 50uA. Bypass to SGND with a 100nF capacitor to reduce noise.
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Functional block diagram
PM6681A
3
Functional block diagram
Figure 3. Functional block diagram
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PM6681A
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Table 2. VFQFPN 5x5x1.0 32L Pitch 0.50
Databook (mm) Dim. Min A A1 A3 b D D2 E E2 e L ddd 0.3 4.85 0.18 4.85 0.8 0 Typ 0.9 0.02 0.2 0.25 5 See exposed pad variations 5 See exposed pad variations 0.5 0.4 0.5 0.05
(2) (2)
Max 1 0.05
0.3 5.15
5.15
Table 3.
Exposed pad variations
(1)(2)D2
E2 Max 3.20 Min 2.90 Typ 3.10 Max 3.20
Min 2.90
Typ 3.10
1. VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead. Very thin: A = 1.00mm Max. 2. Dimensions D2 & E2 are not in accordance with JEDEC.
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Package mechanical data Figure 4. Package dimensions
PM6681A
10/12
PM6681A
Revision history
5
Revision history
Table 4.
Date 02-Nov-2006
Revision history
Revision 1 Initial release Changes
11/12
PM6681A
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